8:30AM to 9:00AM: REGISTRATION

9:00AM to 9:08AM

Welcome of the guests

9:08AM to 9:15AM

Lightening of the lamp

9:10AM to 9:15AM

Welcome address and about the program

Rekha Verma, Vice-Chair, EDS UP Chapter, IIIT Allahabad

9:15AM to 9:25AM

Director’s address

G C Nandi, Director, IIIT Allahabad

9:25AM to 9:35AM

About IEEE EDS UP Chapter

Yogesh Singh Chauhan, Chair, EDS UP Chapter, IITK

9:35AM to 10:35AM

Keynote Lecture

Santanu Mahapatra, IISc Bangalore

10:35 to 10:50AM TEA BREAK (Open area-Quadrangle of CC-3)

TALKS

10:50AM to 11:35AM

FinFET based device circuit co-design: Issues and Challenges

Sudeb Dasgupta, IIT Roorkee

11:35AM to 12:20PM

Negative Capacitance Transistor - Breaking 60mV barrier in conventional CMOS process

Yogesh Singh Chauhan, IIT Kanpur

12:20PM to 1:05PM

III-Nitride visible LEDs: An overview of design, material growth, device fabrication and characterization

S Pal, CEERI Pilani

1:05PM to 2:30 PM LUNCH (Visitor’s Hostel 1)

2:30 PM to 3:15 PM

High-K/Metal-Gate in CMOS Technologies - Integration challenges and anomalous device effects

Nihar Ranjan Mohapatra, IIT Gandhinagar

3:15 PM to 4:00 PM

Crucial aspects for designing high - performance flexible organic thin-film transistors for next generation

Shree Prakash Tiwari, IIT Jodhpur

4:00 PM to 4:50 PM

Atomistic Simulation for Nanoscale Devices

Arun Dubey, Quantumwise (IMS, India)

4:50 PM to 5:00PM

Vote of Thanks

Sitangshu Bhattacharya, IIIT Allahabad

5:00 PM onward: High Tea and discussion (Open area-Quadrangle of CC-3)